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Serial Quad I/O (SQI) Flash Memory
A Microchip Technology Company
SST26VF016 / SST26VF032
Data Sheet
Table 3: Device Operation Instructions for SST26VF016/032 (Continued) (2 of 2)
Instruction
RBPR 13
WBPR 11,13
LBPR 11
Description
Read Block Protection Register
Write Block Protection Register
Lock Down Block Protection
Command
Cycle 1
72H
42H
8DH
Address
Cycle(s) 2
0
0
0
Dummy
Cycle(s)
0
0
0
Data
Cycle(s)
1 to ? m/4
1 to m/4
0
Maximum
Frequency
80 MHz
Register
T3.0
25017
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
One BUS cycle is two clock periods (command, access, or data).
Address bits above the most significant bit of each density can be V IL or V IH.
RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
Device accepts eight-clock command in SPI mode, or two-clock command in SQI mode.
After a power cycle, Read, High-Speed Read, and JEDEC-ID Read instructions input and output cycles are SPI bus
protocol.
Burst length– n = 8 Bytes: Data(00H); n = 16 Bytes: Data(01H); n = 32 Bytes: Data(02H); n = 64 Bytes: Data(03H).
Address is 256 Bytes page align (2’s complement)
The Quad J-ID read wraps the three Quad J-ID Bytes of data until terminated by a low-to-high transition on CE#
Sector Addresses: Use A MS - A 12 , remaining address are don’t care, but must be set to V IL or V IH .
Blocks are 64 KByte, 32 KByte, or 8KByte, depending on location. Block Erase Address: A MS - A 16 for 64 KByte; A MS -
A 15 for 32 KByte; A MS - A 13 for 8 KByte. Remaining addresses are don’t care, but must be set to V IL or V IH .
Requires a prior WREN command.
The Read-Status register is continuous with ongoing clock cycles until terminated by a low-to-high transition on CE#.
Data is written/read from MSB to LSB. MSB = 48 for SST26VF016; 80 for SST26VF032
No Operation (NOP)
The No Operation command only cancels a Reset Enable command. NOP has no impact on any other
command.
?2011 Silicon Storage Technology, Inc.
12
DS-25017A
04/11
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